1. Field of the Invention
The present invention relates to a capacitor circuit and a semiconductor integrated circuit device, and more particularly, to a power supply bypass capacitor circuit for reducing power supply noise in a semiconductor integrated circuit device.
2. Description of the Related Art
In a semiconductor integrated circuit device, it has traditionally been practiced to provide a capacitor circuit between power supplies for noise elimination and other purposes. The prior art capacitor circuit (power supply bypass capacitor) is constructed by forming the power supply wiring pattern and ground pattern of the same shape using different wiring layers formed one above the other in the thickness direction of the substrate and separated in the vertical direction (the thickness direction of the substrate) by the insulating film.
The recent trend in semiconductor integrated circuit devices, despite decreasing feature size and increasing packing density, has the tendency to increase insulating film thickness between wiring layers in order to reduce capacitance on signal lines. With the traditional capacitor circuit design which relies on insulating film thickness, the area that the capacitor circuit occupies will inevitably increase if power supply noise, which is expected to continue to increase in future, is to be reduced sufficiently.
Further, with decreasing feature size and increasing packing density of the semiconductor integrated circuit device, power supply noise is expected to increase in the future due to increased operating clock speed, and there is thus a need to further increase the bypass capacitance between power supplies.
In view of this, there is a need to provide a capacitor circuit that can present a large capacitance without incurring an increase in the area that it occupies, and a semiconductor integrated circuit device having such a capacitor circuit.
The prior art and the problems thereof will be explained later with reference to the accompanying drawings.
An object of the present invention is to provide a capacitor circuit that can present a large capacitance without incurring an increase in the area that it occupies, and a semiconductor integrated circuit device having such a capacitor circuit.
According to the present invention, there is provided a capacitor circuit comprising a first electrode, a second electrode, and a dielectric interposed between the first and second electrodes, wherein a plurality of first wiring lines, each functioning as the first electrode, and a plurality of second wiring lines, each functioning as the second electrode, are formed alternately one adjacent to the other within the same wiring layer.
The wiring layer may include a first wiring layer and a second wiring layer formed one above the other in adjacent fashion in a direction of layer thickness, and the first and second wiring lines in the first wiring layer may be arranged in such a manner as to align respectively with the second and first wiring lines in the second wiring layer in the direction of layer thickness. The wiring layer may include a first wiring layer and a second wiring layer formed one above the other in adjacent fashion in a direction of layer thickness, and the first and second wiring lines in the first wiring layer may be formed in such a manner as to intersect the first and second wiring lines in the second wiring layer.
The wiring layer may include a first wiring layer, a second wiring layer, and a third wiring layer formed one above another in a direction of layer thickness, and wherein a plurality of the first wiring lines and a plurality of the second wiring lines may be formed alternately one adjacent to the other in each of the first and third wiring layers, and may contact for connection to the first and second wiring lines in the first and third wiring layers are formed on the second wiring layer. A plurality of the first wiring lines and a plurality of the second wiring lines may be formed alternately one adjacent to the other in the second wiring layer in such a manner as to intersect the first and second wiring lines in the first and third wiring layers.
The first and second wiring lines may be formed parallel to each other, each with a minimum line width, within the same wiring layer. The dielectric may be an insulating film formed between the first and second wiring lines. Each of the wiring layers may be a metal wiring layer. The first and second wiring lines may be ring wiring lines around a hard macro mounted on a semiconductor integrated circuit device.
Further, according to the present invention, there is also provided a semiconductor integrated circuit device having a first power supply line and a second power supply line, wherein a plurality of the first power supply lines and a plurality of the second power supply lines are formed alternately one adjacent to the other within the same metal wiring layer to construct a capacitor circuit.
The metal wiring layer may include a first metal wiring layer and a second metal wiring layer formed one above the other in adjacent fashion in a direction of layer thickness, and the first and second power supply lines in the first metal wiring layer may be arranged in such a manner as to align respectively with the second and first power supply lines in the second metal wiring layer in the direction of layer thickness. The metal wiring layer may include a first metal wiring layer and a second metal wiring layer formed one above the other in adjacent fashion in a direction of layer thickness, and the first and second power supply lines in the first metal wiring layer may be formed in such a manner as to intersect the first and second power supply lines in the second metal wiring layer.
The metal wiring layer may include a first metal wiring layer, a second metal wiring layer, and a third metal wiring layer formed one above another in a direction of layer thickness, and wherein a plurality of the first power supply lines and a plurality of the second power supply lines may be formed alternately one adjacent to the other in each of the first and third metal wiring layers, and may contact for connection to the first and second power supply lines in the first and third metal wiring layers are formed on the second metal wiring layer. A plurality of the second power supply lines may be formed alternately one adjacent to the other in the second metal wiring layer in such a manner as to intersect the first and second power supply lines in the first and third metal wiring layers.
The first and second power supply lines may be formed parallel to each other, each with a minimum line width, within the same wiring layer. The power supply bypass capacitor circuit may be constructed using ring wiring lines for a hard macro mounted on the semiconductor integrated circuit device.